View SST39SF010A_94648.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
SST39SF010A / 020A / 0405.0V 4Mb (x8) MPF memories
Preliminary Specification
FEATURES:
* Organized as 128K x8 / 256K x8 / 512K x8 * Single 5.0V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) - Standby Current: 30 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Fast Read Access Time: - 45 and 70 ns * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040 * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-pin PLCC - 32-pin TSOP (8mm x 14mm) - 32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A/020A/040 devices write (Program or Erase) with a 5.0V power supply. The SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum Byte-Program time of 20 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a
(c)2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398 1
function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-pin PLCC and 32-pin TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the SectorErase operation will be ignored.
Read
The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram (Figure 4) for further details.
Chip-Erase Operation
The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire memory array to the "1s" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored.
Byte-Program Operation
The SST39SF010A/020A/040 are programmed on a byteby-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased.The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Write Operation Status Detection
The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#
Data# Polling (DQ7)
When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For SecS71147-02-000 5/01 398
(c)2001 Silicon Storage Technology, Inc.
2
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification tor- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.
Product Identification
The product identification mode identifies the device as the SST39SF040, SST39SF010A, or SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users may wish to use the software product identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST39SF010A SST39SF020A SST39SF040 0001H 0001H 0001H B5H B6H B7H
T1.2 398
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data BFH
0000H
Data Protection
The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart.
Software Data Protection (SDP)
The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF010A/ 020A/040 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
3
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers & Latches Y-Decoder CE# OE# WE# DQ7 - DQ0
398 ILL B1.2
Control Logic
I/O Buffers and Data Latches
SST39SF040
WE# WE# WE#
VDD
A12
A15
A16
A18
SST39SF020A
VDD
A12
A15
A16
SST39SF010A
VDD
A12
A15
A16
NC
SST39SF040 SST39SF020A SST39SF010A
NC
SST39SF010A SST39SF020A
A17
NC
A17
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
SST39SF020A SST39SF010A
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
SST39SF040
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-pin PLCC Top View
21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
398 ILL F02.3
DQ1
DQ2
VSS
DQ3
DQ4
DQ5 DQ5
SST39SF040
DQ1
DQ2
VSS
DQ3
DQ4
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC
(c)2001 Silicon Storage Technology, Inc.
DQ6
DQ6
S71147-02-000 5/01
398
4
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
SST39SF040 SST39SF020A A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4
SST39SF010A A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SST39SF010A 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
SST39SF020A OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
389 ILL F01.1
SST39SF040 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Standard Pinout Top View Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM
X
14MM)
SST39SF040 SST39SF020A SST39SF010A
SST39SF010A SST39SF020A
SST39SF040
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
398 ILL F02a.2
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
5
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide 5.0V supply (10%) Unconnected pins.
T2.1 398
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
1. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.3 398
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value.
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
6
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Chip-Erase Software ID Software ID Entry4,5 Exit6 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.2 398
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H Data A0H 80H 80H 90H
4th Bus Write Cycle Addr1 BA2 5555H 5555H Data Data AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH Data 55H 55H
6th Bus Write Cycle Addr1 SAX3 5555H Data 30H 10H
Software ID Exit6
1. Address format A14-A0 (Hex), Addresses A15 - AMS can be VIL or VIH, but no other value, for the Command sequence. 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 4. The device does not remain in Software Product ID Mode if powered down. 5. With AMS-A1 =0; SST Manufacturer's ID= BFH, is read with A0 = 0, SST39SF010A Device ID = B5H, is read with A0 = 1 SST39SF020A Device ID = B6H, is read with A0 = 1 SST39SF040 Device ID = B7H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C
OF
VDD 5.0V10% 5.0V10%
AC CONDITIONS
TEST
30 pF for 45 ns
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns
See Figures 13 and 14
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
7
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V10%
Limits Symbol IDD Parameter Power Supply Current Read Write ISB1 ISB2 ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage 2.4 2.0 VDD-0.3 0.4 25 25 3 100 1 10 0.8 mA mA mA A A A V V V V V Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIH, VDD=VDD Max CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=2.1 mA, VDD=VDD Min IOH=-400 A, VDD=VDD Min
T5.4 398
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T6.1 398
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE
Parameter CI/O
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 398
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.1 398
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
8
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 5.0V10%
SST39SF010A/020A/040-45 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 15 15 0 Min 45 45 45 25 0 0 25 25 Max SST39SF010A/020A/040-70 Min 70 70 70 35 Max Units ns ns ns ns ns ns ns ns ns
T9.3 398
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH TDS TDH TSE TSCE
1 1
Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 40 0
Max 20
Units s ns ns ns ns ns ns ns ns ns ns ns ns
TIDA1
150 25 100
ns ms ms
T10.1 398
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
9
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
TRC ADDRESS AMS-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
398 ILL F03.1
DQ7-0
HIGH-Z
TCLZ
TOH DATA VALID
Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 4: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
398 ILL F04.1
Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
10
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
398 ILL F05.1
Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
D
D#
D#
D
398 ILL F06.1
Note: AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 7: DATA# POLLING TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
Note
TWO READ CYCLES WITH SAME OUTPUTS Note: Toggle bit output is always high first. AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040 398 ILL F07.1
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
398 ILL F08.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
12
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
398 ILL F17.1
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2
398 ILL F09.2
TIDA
TAA BF Device ID
Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040
FIGURE 11: SOFTWARE ID ENTRY
AND
READ
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
13
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# T WHP SW0 SW1 SW2
398 ILL F10.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
14
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
398 ILL F11.1
AC test inputs are driven at VIHT (3.0V) for a logic "1" and VILT (0V) for a logic "0". Measurement reference points for inputs and outputs are VIT (1.5V) and VOT (1.5V). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE VDD TO TESTER RL HIGH
TO DUT CL RL LOW
398 ILL F12.0
FIGURE 14: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
15
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
Start
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
398 ILL F13.1
FIGURE 15: BYTE-PROGRAM ALGORITHM
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
16
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
Internal Timer Byte Program/Erase Initiated
Toggle Bit Byte Program/Erase Initiated
Data# Polling Byte Program/Erase Initiated
Wait TBP, TSCE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
398 ILL F14.0
FIGURE 16: WAIT OPTIONS
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
17
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
Software Product ID Entry Command Sequence
Software Product ID Exit & Reset Command Sequence
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: F0H Address: XXH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Wait TIDA
Load data: 90H Address: 5555H
Load data: F0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
398 ILL F15.1
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
18
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
Chip-Erase Command Sequence Load data: AAH Address: 5555H
Sector-Erase Command Sequence Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 80H Address: 5555H
Load data: 80H Address: 5555H
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 10H Address: 5555H
Load data: 30H Address: SAX
Wait TSCE
Wait TSE
Chip erased to FFH
Sector erased to FFH
398 ILL F16.1
FIGURE 18: ERASE COMMAND SEQUENCE
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
19
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification Device SST39SFxxxA Speed XX Suffix1 XX Suffix2 XX Package Modifier H = 32 pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) P = PDIP U = Unencapsulated die Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 70 = 70 ns Version Device Density 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage S = 5.010%V SST39SF040 Valid combinations SST39SF040-45-4C-NH SST39SF040-70-4C-NH SST39SF040-45-4I-NH SST39SF040-70-4I-NH SST39SF040-45-4C-WH SST39SF040-70-4C-WH SST39SF040-45-4I-WH SST39SF040-70-4I-WH SST39SF040-70-4C-PH
SST39SF010A Valid combinations SST39SF010A-45-4C-NH SST39SF010A-70-4C-NH SST39SF010A-70-4C-U1 SST39SF010A-45-4I-NH SST39SF010A-70-4I-NH SST39SF010A-45-4I-WH SST39SF010A-70-4I-WH SST39SF010A-45-4C-WH SST39SF010A-70-4C-WH SST39SF010A-70-4C-PH
SST39SF020A Valid combinations SST39SF020A-45-4C-NH SST39SF020A-70-4C-NH SST39SF020A-70-4C-U1 SST39SF020A-45-4I-NH SST39SF020A-70-4I-NH
Example:
SST39SF020A-45-4C-WH SST39SF020A-70-4C-WH SST39SF020A-45-4I-WH SST39SF020A-70-4I-WH SST39SF020A-70-4C-PH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
S71147-02-000 5/01 398
(c)2001 Silicon Storage Technology, Inc.
20
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
PACKAGING DIAGRAMS
TOP VIEW
.485 .495 .447 .453 .042 .048
2 1 32
SIDE VIEW
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
BOTTOM VIEW
Optional Pin #1 Identifier
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
Pin # 1 Identifier
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
X
14MM
(c)2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
398
21
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
32
C L
.600 .625
Pin #1 Identifier
.065 .075
1
1.645 1.655 7 4 PLCS.
.530 .550
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
.070 .080
.045 .065
.016 .022
.100 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.2
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398
22

▲Up To Search▲

Price & Availability of SST39SF010A

	To Download SST39SF010A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .